2D placement constraints in digital design

Tom Page; Gisli Thorsteinsson

2D placement constraints in digital design

Tom Page
, Gisli Thorsteinsson

Faculty of Subject Teacher Education

University of Iceland

Research output: Contribution to conference › Paper › peer-review

Abstract

The paper represents problems with 1-D placement as an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuit components within the chip's core area. An inferior placement assignment will not only affect the chip's performance, but might also make it nonmanufacturable by producing excessive wirelength, which is beyond available routing resources. Consequently, a placer must perform the assignment while optimizing a number of objectives to ensure that a circuit meets its performance demands.

Original language	English
Publication status	Published - 2007

Other keywords

1-D placement problem
Extension to 2-D placement
Matrix problem

Cite this

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KW - Extension to 2-D placement

KW - Matrix problem

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2D placement constraints in digital design

Abstract

Other keywords

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Cite this