Fabrication and characterization of field-plated buried-gate SiC MESFETs

Kristoffer Andersson; Mattias Südow; Per Åke Nilsson; Einar Sveinbjörnsson; Hans Hjelmgren; Joakim Nilsson; Johan Ståhl; Herbert Zirath; Niklas Rorsman

doi:10.1109/LED.2006.877285

Fabrication and characterization of field-plated buried-gate SiC MESFETs

Kristoffer Andersson
, Mattias Südow
, Per Åke Nilsson
, Einar Sveinbjörnsson
, Hans Hjelmgren
, Joakim Nilsson
, Johan Ståhl
, Herbert Zirath
, Niklas Rorsman

Faculty of Physical Sciences

University of Iceland

Research output: Contribution to journal › Article › peer-review

Abstract

Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-μ gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz ± 100 kHz indicate an optimum FP length for high linearity operation.

Original language	English
Pages (from-to)	573-575
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	27
Issue number	7
DOIs	https://doi.org/10.1109/LED.2006.877285
Publication status	Published - Jul 2006

Other keywords

Buried-gate
Field-plate (FP)
Microwave power
Silicon carbide (SiC) MESFET

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10.1109/LED.2006.877285

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@article{62b5bc0ef7244bec8ebe1e8ff3de8ebc,

title = "Fabrication and characterization of field-plated buried-gate SiC MESFETs",

abstract = "Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the {"}buried-channel{"} and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-μ gate periphery SiC MESFET. The PAE for this device was 70\% at class AB bias. Two-tone measurements at 3 GHz ± 100 kHz indicate an optimum FP length for high linearity operation.",

keywords = "Buried-gate, Field-plate (FP), Microwave power, Silicon carbide (SiC) MESFET",

author = "Kristoffer Andersson and Mattias S{\"u}dow and Nilsson, \{Per {\AA}ke\} and Einar Sveinbj{\"o}rnsson and Hans Hjelmgren and Joakim Nilsson and Johan St{\aa}hl and Herbert Zirath and Niklas Rorsman",

note = "Funding Information: Manuscript received February 24, 2006; revised April 19, 2006. This work was supported by the Swedish Agency for Innovation Systems (VINNOVA). The review of this letter was arranged by Editor K. Kornegay.",

year = "2006",

month = jul,

doi = "10.1109/LED.2006.877285",

language = "English",

volume = "27",

pages = "573--575",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - Fabrication and characterization of field-plated buried-gate SiC MESFETs

AU - Andersson, Kristoffer

AU - Südow, Mattias

AU - Nilsson, Per Åke

AU - Sveinbjörnsson, Einar

AU - Hjelmgren, Hans

AU - Nilsson, Joakim

AU - Ståhl, Johan

AU - Zirath, Herbert

AU - Rorsman, Niklas

N1 - Funding Information: Manuscript received February 24, 2006; revised April 19, 2006. This work was supported by the Swedish Agency for Innovation Systems (VINNOVA). The review of this letter was arranged by Editor K. Kornegay.

PY - 2006/7

Y1 - 2006/7

N2 - Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-μ gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz ± 100 kHz indicate an optimum FP length for high linearity operation.

AB - Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-μ gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz ± 100 kHz indicate an optimum FP length for high linearity operation.

KW - Buried-gate

KW - Field-plate (FP)

KW - Microwave power

KW - Silicon carbide (SiC) MESFET

UR - https://www.scopus.com/pages/publications/33745648501

U2 - 10.1109/LED.2006.877285

DO - 10.1109/LED.2006.877285

M3 - Article

SN - 0741-3106

VL - 27

SP - 573

EP - 575

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 7

ER -

Fabrication and characterization of field-plated buried-gate SiC MESFETs

Abstract

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