VLSI circuit partitioning at system, board & chip levels

This paper provides an outline of system-level partitioning in very large-scale integration (VLSI) design. The objective of which is to optimize system performance while minimizing the number of circuits required. The major constraints in this phase include: constant board size and fixed terminal counts. Further to this, optimizing the performance by minimizing the number of integrated circuits with fixed chip dimensions and terminal counts. The paper concludes with minimizing the number of interconnection nets cut by partitioning and avoiding cutting critical nets by the partitioning.